View AD8151_5207279.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

rev. 0 information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD8151 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ?analog devices, inc., 2001 functional block diagram cs re d a we update reset 7 5 second rank 17 7-bit latch 33 17 differential switch matrix input decoders 17 outp outn 33 33 inp inn AD8151 first rank 17 7-bit latch 17 output address decoder features low cost 33 17, fully differential, nonblocking array 3.2 gb/s per port nrz data rate wide power supply range: +3.3 v, ?.3 v low power 425 ma (outputs enabled) 35 ma (outputs disabled) lv pecl and lv ecl compatible cmos/ttl-level control inputs: 3 v to 5 v low jitter no heat sinks required drives a backplane directly programmable output current optimize termination impedance user-controlled voltage at the load minimize power dissipation individual output disable for busing and reducing power double row latch buffered inputs available in 184-lead lqfp applications high-speed serial backplane routing to oc-48 with fec fiber optic network switching fiber channel lvds 33 17, 3.2 gb/s digital crosspoint switch * patent pending. x stream is a trademark of analog devices, inc. product description AD8151 is a member of the x stream line of products and is a breakthrough in digital switching, offering a large switch array (33 17) on very little power, typically less than 1.5 w. addi- tionally, it operates at data rates in excess of 3.2 gb/s per port, making it suitable for sonet oc-48 with 8b/10b forward error correction (fec). further, the pricing of the AD8151 makes it affordable enough to be used for lower data rates as well. the AD8151? flexible supply voltages allow the user to operate with either pecl or ecl data levels and will operate down to 3.3 v for further power reduction. the control interface is cmos/ ttl compatible (3 v to 5 v). its fully differential signal path reduces jitter and crosstalk while allowing the use of smaller single-ended voltage swings. the AD8151 is offered in a 184-lead lqfp package that operates over the extended co mmercial temperature ra nge of 0 c to 85 c. figure 1. eye pattern, 3.2 gb/s, prbs 23 stream a
? rev. 0 AD8151?pecifications (@ 25 c, v cc = 3.3 v to 5 v, v ee = 0 v, r l = 50 (see tpc 22), i out = 16 ma, unless otherwise noted.) parameter conditions min typ max unit dynamic performance max data rate/channel (nrz) 2.5 3.2 gb/s channel jitter data rate = 3.2 gb/s 52 ps p-p rms channel jitter 8ps propagation delay input to output 650 ps propagation delay match 50 100 ps output rise/fall time 20% to 80% 100 ps input characteristics input voltage swing single-ended 200 1000 mv p-p input bias current 2 a input capacitance 2pf input v in high v cc ?1.2 v cc v input v in low v cc ?2.4 v cc ?1.4 v output characteristics output voltage swing differential (see tpc 22) 800 mv p-p output voltage range v cc ?1.8 v cc v output current 5 25 ma output capacitance 2pf output v out high v cc ?1.8 v output v out low v cc v power supply operating range pecl, v cc v ee = 0 v 3.0 5.25 v ecl, v ee v cc = 0 v ?.25 ?.0 v v dd 35v v ss 0v quiescent current v dd 2ma v ee all outputs enabled, i out = 16 ma 425 ma t min to t max 450 ma all outputs disabled 35 ma thermal characteristics operating temperature range 0 85 c ja 30 c/w logic input characteristics v dd = 3 v dc to 5 v dc input v in high 1.9 v dd v input v in low 0 0.9 v
AD8151 ? rev. 0 caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD8151 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device maximum power dissipation the maximum power that can be safely dissipated by the a d8151 is limited by the associated rise in junction temperature. the maximum safe junction temperature for plastic encapsulated devices is determined by the glass transition temperature of the plastic, approximately 150 c. temporarily exceeding this limit may cause a shift in parametric performance due to a change in the stresses exerted on the die by the package. exceeding a junction temperature of 175 c for an extended period can result in device failure. to ensure proper operation, it is necessary to observe the maxi- mum power derating curves shown in figure 2. ambient temperature C c maximum power dissipation C watts C10 0 102030 405060708090 2.0 3.0 4.0 5.0 6.0 t j = 150 c 1.0 figure 2. maximum power dissipation vs. temperature absolute maximum ratings 1 supply voltage v dd ? ee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.5 v v cc ?v ee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v v dd ?v ss . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v v ss ?v ee . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v v ss ?v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v v dd ?v cc . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 v internal power dissipation 2 AD8151 184-lead plastic lqfp (st) . . . . . . . . . . . . 4.2 w differential input voltage . . . . . . . . . . . . . . . . . . . . . . . . 2.0 v storage temperature range . . . . . . . . . . . . ?5 c to +125 c lead temperature range (soldering 10 sec) . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this speci?ation is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 speci?ation is for device in free air (t a = 25 c): 184-lead plastic lqfp (st): ja = 30 c/w. ordering guide temperature package package model range description option AD8151ast 0 c to 85 c 184-lead plastic lqfp st-184 (20 mm 20 mm) AD8151-eval evaluation board
AD8151 ? rev. 0 pin configuration 184 183 182 181 180 179 178 177 176 175 174 173 171 170 169 168 167 166 165 164 163 162 172 161 160 159 157 156 155 154 153 152 158 151 150 149 147 146 145 144 143 142 141 140 139 148 59 60 61 62 63 64 65 66 67 68 47 48 49 50 51 52 53 54 55 56 57 58 69 70 71 72 74 75 76 77 78 73 79 80 81 82 84 85 86 87 83 88 89 90 91 92 5 4 3 2 7 6 9 8 1 14 13 12 11 16 15 17 10 19 18 23 22 21 20 25 24 27 26 29 28 32 31 30 34 33 36 35 40 39 38 37 41 43 42 45 44 46 pin 1 identifier top view (not to scale) v ee in19n in19p v ee in18n in18p v ee in17n in17p v ee in16n in16p v ee v cc v dd reset cs re we update a0 a1 a2 a3 a4 d0 d1 d2 d3 d4 d5 d6 v ss ref v ee ref v cc v ee in15n in15p v ee in14n in14p v ee in13n in13p v ee v ee out15n out15p v ee a15 out14n out14p v ee a14 out13n out13p v ee a13 out12n out12p v ee a12 out11n out11p v ee a11 out10n out10p v ee a10 out09n out09p v ee a9 out08n out08p v ee a8 out07n out07p v ee a7 out06n out06p v ee a6 out05n out05p v ee a5 out04n out04p v ee a4 out03n out03p v ee a3 out02n out02p v ee a2 out01n out01p v ee v ee in20p in20n v ee in21p in21n v ee in22p in22n v ee in23p in23n v ee in24p in24n v ee in25p in25n v ee in26p in26n v ee in27p in27n v ee in28p in28n v ee in29p in29n v ee in30p in30n v ee in31p in31n v ee in32p in32n v ee v cc v ee out16n out16p v ee a16 v ee v ee in12n in12p v ee in11n in11p v ee in10n in10p v ee in09n in09p v ee in08n in08p v ee in07n in07p v ee in06n in06p v ee in05n in05p v ee in04n in04p v ee in03n in03p v ee in02n in02p v ee in01n in01p v ee in00n in00p v ee v cc v ee a0 out00p out00n v ee a1 v ee 122 137 138 132 133 134 135 130 131 129 136 127 128 123 124 125 126 120 121 118 119 116 117 113 114 115 111 112 109 110 108 105 106 107 104 102 103 100 101 95 96 97 98 99 93 94 AD8151 184l lqfp
AD8151 ? rev. 0 pin function descriptions pin no. signal type description 1, 4, 7, 10, 13, 16, 19, 22, 25, 28, 31, v ee power supply most negative pecl supply (common with other 34, 37, 40, 42, 46, 47, 92, 93, 99, 102, points labeled v ee ) 105, 108, 111, 114, 117, 120, 123, 126, 129, 132, 135, 138, 139, 142, 145, 148, 172, 175, 178, 181, 184 2 in20p pecl/ecl high-speed input 3 in20n pecl/ecl high-speed input complement 5 in21p pecl/ecl high-speed input 6 in21n pecl/ecl high-speed input complement 8 in22p pecl/ecl high-speed input 9 in22n pecl/ecl high-speed input complement 11 in23p pecl/ecl high-speed input 12 in23n pecl/ecl high-speed input complement 14 in24p pecl/ecl high-speed input 15 in24n pecl/ecl high-speed input complement 17 in25p pecl/ecl high-speed input 18 in25n pecl/ecl high-speed input complement 20 in26p pecl/ecl high-speed input 21 in26n pecl/ecl high-speed input complement 23 in27p pecl/ecl high-speed input 24 in27n pecl/ecl high-speed input complement 26 in28p pecl/ecl high-speed input 27 in28n pecl/ecl high-speed input complement 29 in29p pecl/ecl high-speed input 30 in29n pecl/ecl high-speed input complement 32 in30p pecl/ecl high-speed input 33 in30n pecl/ecl high-speed input complement 35 in31p pecl/ecl high-speed input 36 in31n pecl/ecl high-speed input complement 38 in32p pecl/ecl high-speed input 39 in32n pecl/ecl high-speed input complement 41, 98, 149, 171 v cc power supply most positive pecl supply (common with other points labeled v cc ) 43 out16n pecl/ecl high-speed output complement 44 out16p pecl/ecl high-speed output 45 v ee a16 power supply m ost negative pecl supply (unique to this output) 48 out15n pecl/ecl high-speed output complement 49 out15p pecl/ecl high-speed output 50 v ee a15 power supply most negative pecl supply (unique to this output) 51 out14n pecl/ecl high-speed output complement 52 out14p pecl/ecl high-speed output 53 v ee a14 power supply most negative pecl supply (unique to this output) 54 out13n pecl/ecl high-speed output complement 55 out13p pecl/ecl high-speed output 56 v ee a13 power supply most negative pecl supply (unique to this output) 57 out12n pecl/ecl high-speed output complement 58 out12p pecl/ecl high-speed output 59 v ee a12 power supply most negative pecl supply (unique to this output) 60 out11n pecl/ecl high-speed output complement 61 out11p pecl/ecl high-speed output
AD8151 ? rev. 0 pin no. signal type description 62 v ee a11 power supply most negative pecl supply (unique to this output) 63 out10n pecl/ecl high-speed output complement 64 out10p pecl/ecl high-speed output 65 v ee a10 power supply most negative pecl supply (unique to this output) 66 out09n pecl/ecl high-speed output complement 67 out09p pecl/ecl high-speed output 68 v ee a9 power supply most negative pecl supply (unique to this output) 69 out08n pecl/ecl high-speed output complement 70 out08p pecl/ecl high-speed output 71 v ee a8 power supply most negative pecl supply (unique to this output) 72 out07n pecl/ecl high-speed output complement 73 out07p pecl/ecl high-speed output 74 v ee a7 power supply most negative pecl supply (unique to this output) 75 out06n pecl/ecl high-speed output complement 76 out06p pecl/ecl high-speed output 77 v ee a6 power supply most negative pecl supply (unique to this output) 78 out05n pecl/ecl high-speed output complement 79 out05p pecl/ecl high-speed output 80 v ee a5 power supply most negative pecl supply (unique to this output) 81 out04n pecl/ecl high-speed output complement 82 out04p pecl/ecl high-speed output 83 v ee a4 power supply most negative pecl supply (unique to this output) 84 out03n pecl/ecl high-speed output complement 85 out03p pecl/ecl high-speed output 86 v ee a3 power supply most negative pecl supply (unique to this output) 87 out02n pecl/ecl high-speed output complement 88 out02p pecl/ecl high-speed output 89 v ee a2 power supply most negative pecl supply (unique to this output) 90 out01n pecl/ecl high-speed output complement 91 out01p pecl/ecl high-speed output 94 v ee a1 power supply most negative pecl supply (unique to this output) 95 out00n pecl/ecl high-speed output complement 96 out00p pecl/ecl high-speed output 97 v ee a0 power supply most negative pecl supply (unique to this output) 100 in00p pecl/ecl high-speed input 101 in00n pecl/ecl high-speed input complement 103 in01p pecl/ecl high-speed input 104 in01n pecl/ecl high-speed input complement 106 in02p pecl/ecl high-speed input 107 in02n pecl/ecl high-speed input complement 109 in03p pecl/ecl high-speed input 110 in03n pecl/ecl high-speed input complement 112 in04p pecl/ecl high-speed input 113 in04n pecl/ecl high-speed input complement 115 in05p pecl/ecl high-speed input 116 in05n pecl/ecl high-speed input complement 118 in06p pecl/ecl high-speed input 119 in06n pecl/ecl high-speed input complement 121 in07p pecl/ecl high-speed input 122 in07n pecl/ecl high-speed input complement
AD8151 ? rev. 0 pin no. signal type description 124 in08p pecl/ecl high-speed input 125 in08n pecl/ecl high-speed input complement 127 in09p pecl/ecl high-speed input 128 in09n pecl/ecl high-speed input complement 130 in10p pecl/ecl high-speed input 131 in10n pecl/ecl high-speed input complement 133 in11p pecl/ecl high-speed input 134 in11n pecl/ecl high-speed input complement 136 in12p pecl/ecl high-speed input 137 in12n pecl/ecl high-speed input complement 140 in13p pecl/ecl high-speed input 141 in13n pecl/ecl high-speed input complement 143 in14p pecl/ecl high-speed input 144 in14n pecl/ecl high-speed input complement 146 in15p pecl/ecl high-speed input 147 in15n pecl/ecl high-speed input complement 150 v ee ref r-program connection point for output logic pull-down programming resistor (must be connected to v ee ) 151 ref r-program connection point for output logic pull-down programming resistor 152 v ss power supply most negative control logic supply 153 d6 ttl enable/ disable output 154 d5 ttl (32) msb input select 155 d4 ttl (16) 156 d3 ttl (8) 157 d2 ttl (4) 158 d1 ttl (2) 159 d0 ttl (1) lsb input select 160 a4 ttl (16) msb output select 161 a3 ttl (8) 162 a2 ttl (4) 163 a1 ttl (2) 164 a0 ttl (1) lsb output select 165 update ttl second rank program 166 we ttl first rank program 167 re ttl enable readback 168 cs ttl enable chip to accept programming 169 reset ttl disable all outputs (hi-z) 170 v dd power supply most positive control logic supply 173 in16p pecl/ecl high-speed input 174 in16n pecl/ecl high-speed input complement 176 in17p pecl/ecl high-speed input 177 in17n pecl/ecl high-speed input complement 179 in18p pecl/ecl high-speed input 180 in18n pecl/ecl high-speed input complement 182 in19p pecl/ecl high-speed input 183 in19n pecl/ecl high-speed input complement
AD8151 ? rev. 0 typical performance characteristics tpc 1. eye pattern 2.5 gb/s, prbs 23 150mv/div 20ps/div p-p = 43ps std dev = 8ps tpc 2. jitter @ 2.5 gb/s, prbs 23 100 90 80 70 60 50 40 30 20 10 0 0.5 data rate C gb/s eye width C % 1.0 1.5 2.0 2.5 3.0 3.5 % eye width = (clock period C jitter p-p) clock period 100 tpc 3. eye width vs. data rate, prbs 23 tpc 4. eye pattern 3.2 gb/s, prbs 23 150mv/div 20ps/div p-p = 53ps std dev = 8ps tpc 5. jitter @ 3.2 gb/s, prbs 23 100 90 80 70 60 50 40 30 20 10 0 0.5 data rate C gb/s eye height C % % eye height = (v out @ data rate) v out @ 0.5gb/s 100 1.0 1.5 2.0 2.5 3.0 3.5 tpc 6. eye height vs. data rate, prbs 23
AD8151 ? rev. 0 100 90 80 70 60 50 40 30 20 10 0 1.0 data rate C gb/s jitter C ps 1.5 2.0 2.5 3.0 3.5 standard deviation peak-peak jitter tpc 7. jitter vs. data rate, prbs 23 150mv/div 100ps/div p-p = 38ps std dev = 7.7ps tpc 8. crosstalk, 2.5 gb/s, prbs 23, attack signal is off 150mv/div 100ps/div p-p = 70ps std dev = 8ps tpc 9. crosstalk, 2.5 gb/s, prbs 23, attack signal is on temperature C c 0 100 90 80 70 60 50 40 30 20 10 0 102030405060708090 jitter C ps 2.5gb/s std dev 3.2gb/s std dev 2.5gb/s jitter 3.2gb/s jitter tpc 10. jitter vs. temperature, prbs 23 150mv/div 75ps/div p-p = 32ps std dev = 4.7ps tpc 11. crosstalk, 3.2 gb/s, prbs 23, attack signal is off 150mv/div 75ps/div p-p = 70ps std dev = 9ps tpc 12. crosstalk, 3.2 gb/s, prbs 23, attack signal is on
AD8151 ?0 rev. 0 150mv/div 1.4ns/div tpc 13. response, 2.5 gb/s, 32-bit pattern 1111 1111 0000 0000 0101 0101 0011 0011 input amplitude C v 0 100 90 80 70 60 50 40 30 20 10 0.2 0.3 0.5 0.6 0.7 0.8 0.9 1 0.4 p-p jitter C ps 2.5gb/s jitter 3.2gb/s jitter tpc 14. jitter vs. single-ended input amplitude, prbs 23 3.2gb/s 2.5gb/s 100 90 80 70 60 50 40 30 20 10 0 p-p jitter C ps v ih C v C 1.6 C 1.4 C 1.2 C 1.0 C 0.8 C 0.6 C 0.4 C 0.2 0 0.2 0.4 0.6 tpc 15. jitter vs. v ih , prbs 23 150mv/div 1.1ns/div tpc 16. response, 3.2 gb/s, 32-bit pattern 1111 1111 0000 0000 0101 0101 0011 0011 100 90 80 70 60 50 40 30 20 10 0 p-p jitter C ps 3.2gb/s 2.5gb/s v ee C v C 5.0 C 4.8 C 4.6 C 4.4 C 4.2 C 4.0 C 3.8 C 3.6 C 3.4 C 3.2 C 3.0 tpc 17. jitter vs. supply, prbs 23 100 90 80 70 60 50 40 30 20 10 0 C 1.4 C 1.2 C 1.0 C 0.8 C 0.6 C 0.4 C 0.2 0 0.2 3.2gb/s 2.5gb/s v oh C v p-p jitter C ps tpc 18. jitter vs. v oh , prbs 23, output amplitude = 0.4 v single-ended
AD8151 ?1 rev. 0 100 90 80 70 60 50 40 30 20 10 0 550 570 590 610 630 650 670 690 710 730 frequency propagation delay C ps tpc 19. variation in channel-to-channel delay, all 561 points 2.5gb/s 3.2gb/s 100 90 80 70 60 50 40 30 20 10 0 5 p-p jitter C ps output current C ma 10 15 20 25 tpc 20. jitter vs. i out , prbs 23 200 150 100 50 0 C 50 C 100 C 150 C 200 C 100 C 80 C 60 C 40 C 20 0 20 40 60 80 100 normalized temperature C c propagation delay C ps tpc 21. propagation delay, normalized at 25 c vs. temperature v cc v ee 1.65k 105 1.65k 49.9 v tt prbs generator v tt 49.9 AD8151 v cc v ee in out p n p high-speed sampling oscilloscope 50 50 v cc = 0v, v ee = C 3.3v, v tt = C 1.6v, v dd = 5v, v ss = 0v r set = 1.54k , i out = 16ma, v oh = C 0.8v, v ol = C 1.2v v in = 0.8v p-p except as noted data out data out C 6db n C 6db tpc 22. test circuit
AD8151 ?2 rev. 0 control interface truth tables the following are truth tables for the control interface. table i. basic control functions control pins reset cs we re update function 0 x x x x global reset. reset all second rank enable bits to zero (disable all outputs). 1 1 x x x control disable. ignore all logic (but the signal matrix still functions as programmed). d[6:0] are high-impedance. 1 0 0 x x single output preprogram. write input con?uration data from data bus d[6:0]. into ?st rank of latches for the output selected by the output address bus a[4:0]. 1 0 x 0 x single output readback. readback input con?uration data from second rank of latches onto data bus d[6:0] for the single output selected by the o utput address bus a[4:0]. 1 0 x x 0 global update. copy input con?uration data from all 17 ?st rank latches into second rank of latches, updating signal matrix connections for all outputs. 1 0 0 1 0 transparent write and update. it is possible to write data directly onto rank two. this simpli?s logic when synchronous signal matrix updating is not necessary. table ii. address/data examples output address pins enable input address pins msb?sb bit msb?sb a4 a3 a2 a1 a0 d6/e d5 d4 d3 d2 d1 d0 function 00000x 000000 lower address/data range. connect output #00 (a[4:0] = 00000) to input #00 (d[5:0] = 000000). 10000x 100000 upper address/data range. connect output #16 (a[4:0] = 10000) to input #32 (d[5:0] = 100000). 1 enable output. connect selected output (a[4:0] = 0 to 16) to designated input (d[5:0] = 0 to 32) and enable output (d6 = 1). 0 xxxxxx disable output. disable speci?d output (d6 = 0). 10001x broadcast connection. connect all 17 outputs to same designated input and set all 17 enable bits to the value of d6. readback is not possible with the broadcast address. 10010x 100001 reserved. any address or data code greater or equal to these are reserved for future expansion or factory testing. * the binary output number may also be the broadcast connection designator, 10001.
AD8151 ?3 rev. 0 control interface timing diagrams cs input t asw t ahw t dsw we input a[4:0] inputs d[6:0] inputs t csw t wp t chw t dhw figure 3. first rank write cycle table iii. first rank write cycle symbol parameter conditions min typ max unit t csw setup time chip select to write enable t a = 25 c0 ns t asw address to write enable v dd = 5 v 0 ns t dsw data to write enable v cc = 3.3 v 15 ns t chw hold time chip select from write enable 0 ns t ahw address from write enable 0 ns t dhw data from write enable 0 ns t wp width of write enable pulse 15 ns previous rank 2 data cs input update input enabling out[0:16][n:p] outputs toggle out[0:16][n:p] outputs disabling out[0:16][n:p] outputs data from rank 1 t csu t uoe t chu data from rank 1 data from rank 2 t uw t uod t uot figure 4. second rank update cycle table iv. second rank update cycle symbol parameter conditions min typ max unit t csu setup time chip select to update t a = 25 c0 ns t chu hold time chip select from update v dd = 5 v 0 ns t uoe output enable times update to output enable v cc = 3.3 v 25 40 ns t uot output toggle times update to output reprogram 25 40 ns t uod output disable times update to output disabled 25 30 ns t uw width of update pulse 15 ns
AD8151 ?4 rev. 0 cs input update input enabling out[0:16][n:p] outputs disabling out[0:16][n:p] outputs we input t csu t uot t uoe t wot t whu input {data 1} input {data 1} input {data 2} input {data 0} t chu t uw t wod figure 5. first rank write cycle and second rank update cycle table v. first rank write cycle and second rank update cycle symbol parameter conditions min typ max unit t csu setup time chip select to update t a = 25 c0 ns t chu hold time chip select from update v dd = 5 v 0 ns t uoe output enable times update to output enable v cc = 3.3 v 25 40 ns t woe * write enable to output enable 25 40 ns t uot output toggle times update to output reprogram 25 30 ns t wot write enable to output reprogram 25 30 ns t uod * output disable times update to output disabled 25 30 ns t wod write enable to output disabled 25 30 ns t whu setup time write enable to update 10 ns t uw width of update pulse 15 ns * not shown. a[4:0] inputs t csr d[6:0] outputs t rde t aa t rha cs input re input addr 1 addr 2 data {addr1} data {addr2} t chr t rdd figure 6. second rank readback cycle table vi. second rank readback cycle symbol parameter conditions min typ max unit t csr setup time chip select to read enable t a = 25 c0 ns t chr hold time chip select from read enable v dd = 5 v 0 ns t rha address from read enable v cc = 3.3 v 5 ns t rde enable time data from read enable 10 k ? 15 ns t aa access time data from address 20 pf on d[6:0] 15 ns t rdd release time data from read enable bus 15 30 ns
AD8151 ?5 rev. 0 disabling out[0:16][n:p] outputs reset input t tod t tw figure 7. asynchronous reset table vii. asynchronous reset symbol parameter conditions min typ max unit t tod disable time output disable from reset t a = 25 c2530ns t tw width of reset pulse v dd = 5 v 15 ns v cc = 3.3 v control interface programming example the following conservative pattern connects all outputs to input number 7, except output 16 which is connected to input number 32. the vector clock period, t 0 is 15 ns. it is possible to accelerate the execution of this pattern by deleting vectors 1, 4, 7, and 9. table viii. basic test pattern vector no. reset cs we re update a[4:0] d[6:0] comments 0 0 1 1 1 1 xxxxx xxxxxxx disable all outputs 1 1 1 1 1 1 xxxxx xxxxxxx 2 1 0 1 1 1 10001 1000111 all outputs to input #07 3 1 0 0 1 1 10001 1000111 write to first rank 4 1 0 1 1 1 10001 1000111 5 1 0 1 1 1 10000 1100000 output #16 to input #32 6 1 0 0 1 1 10000 1100000 write to first rank 7 1 0 1 1 1 10000 1100000 8 1 0 1 1 0 xxxxx xxxxxxx transfer to second rank 9 1 0 1 1 1 xxxxx xxxxxxx 10 1 1 1 1 1 xxxxx xxxxxxx disable interface
AD8151 ?6 rev. 0 update 7 0 1 2 16 33 1 of 33 decoders 1 of 17 decoders we d[0:6] re a[0:4] rank 1 rank 2 17 rows of 7-bit latches reset to 17 33 switch matrix 7 33 7 33 7 33 7 7 7 7 0 1 2 16 7 7 7 7 7 7 7 7 7 figure 8. control interface (simpli?d schematic) AD8151 control interface the AD8151 control interface receives and stores the desired connection matrix for the 33 input and 17 output signal pairs. the interface consists of 17 rows of double-rank 7-bit latches, one row for each output. the 7-bit data word stored in each of these latches indicates to which (if any) of the 33 inputs the output will be connected. one output at a time can be preprogrammed by addressing the output and writing the desired connection data into the ?st rank of latches. this process can be repeated until each of the desired output changes has been preprogrammed. all output connections can then be programmed at once by passing the data from the ?st rank of latches into the second rank. the output connections always reflect the data programmed into the second rank of latches, and do not change until the ?st rank of data is passed into the second rank. if necessary for system veri?ation, the data in the second rank of latches can be read back from the control interface. at any time, a reset pulse can be applied to the control interface to globally reset the appropriate second rank data bits, disabling all 17 signal output pairs. this feature can be used to avoid output bus contention on system start-up. the contents of the ?st rank remain unchanged. the control interface pins are connected via logic-level transla- tors. these translators allow programming and readback of the control interface using logic levels different from those in the signal matrix. in order to facilitate multiple chip address decoding, there is a chip-select pin. all logic signals except the reset pulse are ig nored unless the chip select pin is active. the chip select pin disables only the control logic interface, and does not change the opera- tion of the signal matrix. the chip select pin does not power down any of the latches, so any data programmed in the latches is preserved. all control pins are level-sensitive, not edge-triggered. control pin description a[4:0] inputs output address pins. the binary encoded address applied to these ?e input pins determines which one of the seventeen outputs is being programmed (or being read back). the most signi?ant bit is a4. d[6:0] inputs/outputs input con?uration data pins. in write mode, the binary encoded data applied to pins d[6:0] determine which one of 33 inputs is to be connected to the output speci?d with the a[4:0] pins. the most signi?ant bit is d5, and the least signi?ant bit is d0. bit d6 is the e nable bit, setting the speci?d output sig- nal pair to an enabled state if d6 is logic high, or disabled to a high-impedance state if d6 is logic low. in readback mode, pins d[6:0] are low-impedance outputs indi- cating the data word stored in the second rank for the output speci?d with the a[4:0] pins. the readback drivers were designed to drive high impedances only, so external drivers connected to the d[6:0] should be disabled during readback mode. we input first rank write enable. forcing this pin to logic low al lows the data on pins d[6:0] to be stored in the ?st rank latch for the output speci?d by pins a[4:0]. the we pin must be returned to a logic high state after a write cycle to avoid overwriting the ?st rank data. update input second rank write enable. forcing this pin to logic low allows the data stored in all 17 ?st rank latches to be transferred to the second rank latches. the signal connection matrix will be repro- grammed when the second rank data is changed. this is a global pin, transferring all 17 rows of data at once. it is not necessary to program the address pins. it should be noted that after initial power-up of the device, the ?st rank data is unde?ed. it may be desirable to preprogram all seventeen outputs before per forming the ?st update cycle. re input second rank read-enable. forcing this pin to logic low enables the output drivers on the bidirectional d[6:0] pins, entering the readback mode of operation. by selecting an output address with the a[4:0] pins and forcing re to logic low, the 7-bit data stored in the second rank latch for that output address will be written to d[6:0] pins. data should not be written to the d[6:0] pins externally while in readback mode. the re and we pins are not exclusive, and may be used at the same time, but data should not be written to the d[6:0] pins from external sources while in readback mode. cs input chip-select. this pin must be forced to logic low in order to program or receive data from the logic interface, with the exception of the reset pin, described below. this pin has no effect on the signal pairs and does not alter any of the stored control data. reset input global output disable pin. forcing the reset pin to logic low will reset the enable bit, d6, in all 17 second rank latches, regardless of the state of any other pins. this has the effect of immediately disabling the 17 output signal pairs in the
AD8151 ?7 rev. 0 matrix. it is useful to momentarily hold reset at a logic low state when powering up the AD8151 in a system that has mul- tiple output signal pairs connected together. failure to do this may result in several signal outputs contending after power-up. the reset pin is not gated by the state of the chip-select pin, cs . it should be noted that the reset pin does not program the ?st rank, which will contain unde?ed data after power-up. control interface translators the AD8151 control interface has two supply pins, v dd and v ss . the potential between the positive logic supply v dd and the negative logic supply v ss must be at least 3 v and no more than 5 v. regardless of supply, the logic threshold is approxi- mately 1.6 v above v ss , allowing the interface to be used with most cmos and ttl logic drivers. the signal matrix supplies, v cc and v ee , can be set indepen- dent of the voltage on v dd and v ss , with the constraints that (v dd ? ee ) 10 v. these constraints will allow operation of the c ontrol interface on 3 v or 5 v while the signal matrix is operated on +3.3 v or +5 v pecl, or ?.3 v or ? v ecl. circuit description the AD8151 is a high-speed 33 17 differential crosspoint switch designed for data rates up to 3.2 gb/s per channel. the AD8151 supports pecl-compatible input and output levels when operated from a 5 v supply (v cc = 5 v, v ee = gnd) or ecl-c ompatible levels w hen operated from a ? v supply (v cc = gnd, v ee = ? v). to save power, the AD8151 can run from a +3.3 v supply to interface with low-voltage pecl circuits or a ?.3 v supply to interface with low-voltage ecl circuits. the AD8151 utilizes differential current mode outputs with individual disable control, which facilitates busing together the outputs of multiple AD8151s to assemble larger switch arrays. this feature also reduces sys- tem crosstalk and can greatly reduce power dissipation in a large switch array. a single external resistor programs the current for all enabled output stages, allowing for user control over output levels with different output termination schemes and transmis- sion line characteristic impedances. high-speed data inputs (inxxp, inxxn) the AD8151 has 33 pairs of differential voltage-mode inputs. the common-mode input range extends from the positive sup- ply voltage (v cc ) down to include standard ecl or pecl input levels (v cc ?2 v). the minimum differential input voltage is 200 mv. unused inputs may be connected directly to any level within the allowed common-mode input range. a simpli?d schematic of the input circuit is shown in figure 9. v cc inxxp inxxn v ee figure 9. simpli?d input circuit in order to maintain signal ?elity at the high data rates sup ported by the AD8151, the input transmission lines should be terminated as close to the input pins as possible. the preferred input termi- nation structure will depend primarily on the application and the output circuit of the data source. standard ecl compo- nents have open emitter outputs that require pull-down resistors. three input termination networks suitable for this type of source are shown in figure 10. the characteristic impedance of the trans- mission line is shown as z o . the resistors, r1 and r2, in the thevenin termination are chosen to synthesize a v tt source with an output resistance of z o and an open-circuit output volt- age equal to v cc ?2 v. the load resi stors (r l ) in the differential termination scheme are needed to bias the emitter followers of the ecl source. v cc inxxp inxxn z o z o z o z o ecl source v tt = v cc C 2v (a) v cc inxxp inxxn z o z o r2 r2 r1 r1 v ee ecl source v cc C 2v (b) v cc inxxp inxxn z o r l z o 2z o r l v ee ecl source (c) figure 10. a d8151 input termination from ecl/pecl sources: a) parallel termination using v tt supply, b) thevenin equivalent termination, c) differential termination if the AD8151 is driven from a current mode output stage such as another AD8151, the input termination should be chosen to accommodate that type of source, as explained in the fol- lowing section. high-speed data outputs (outyyp, outyyn) the AD8151 has 17 pairs of differential current-mode outputs. the output circuit, shown in figure 11, is an open-collector npn current switch with resistor-programmable tail current and output compliance extending from the positive supply voltage (v cc ) down to standard ecl or pecl output levels (v cc ?2 v). the outputs may be disabled individually to permit outputs from multiple AD8151s to be connected directly. since the output currents of multiple enabled output stages connected in this way sum, care should be taken to ensure that the out- put compliance limit is not exceeded at any time; this can be achieved by disabling the active output driver before enabling any inactive driver.
AD8151 ?8 rev. 0 v cc v ee disable i out outyyp outyyn v cc C 2v v ee figure 11. simpli?d output circuit to ensure proper operation, all outputs (including unused output) must be pulled high using external pull-up networks to a level within the output compliance range. if outputs from multiple AD8151s are wired together, a single pull-up network may be used for each output bus. the pull-up network should be chosen to keep the output voltage levels within the output compliance range at all times. recommended pull-up networks to produce pecl/ecl 100 k ? and 10 k ? compatible outputs are shown in figure 12. alternatively, a separate supply can be used to provide v com ; making r com and d com unnecessary. v cc r com v com r l outyyn outyyp AD8151 r l d com v cc v com r l outyyn outyyp AD8151 r l figure 12. o utput pull-up networks: a) ecl 100 k ? , b) ecl 10 k ? the output levels are simply: v oh = v com v ol = v com ?i out r l v swing = v oh ?v ol = i out r l v com = v cc ?i out r com ( 100 k ? mode ) v com = v cc ?v ( d com ) ( 10 k ? mode ) the common-mode adjustment element (r com or d com ) may be omitted if the input range of the receiver includes the positive supply voltage. the bypass capacitors reduce common-mode perturbations by providing an ac short from the common nodes (v com ) to ground. when busing together the outputs of multiple AD8151s or when running at high data rates, double termination of its outputs is recommended to mitigate the impact of reflections due to open transmission line stubs and the lumped capacitance of the AD8151 output pins. a possible connection is shown in figure 13; the bypass capacitors provide an ac short from the common nodes of the termination resistors to ground. to maintain signal ?elity at high data rates, the stubs connecting the output pins to the output transmission lines or load resistors should be as short as possible. v cc r com v com r l outyyn outyyp AD8151 r l z o z o outyyn outyyp AD8151 z o z o r l r l receiver figure 13. double termination of AD8151 outputs in this case, the output levels are: v oh = v com (1/4) i out r l v ol = v com (3/4) i out r l v swing = v oh v ol = (1/2) i out r l output current set pin (ref) a simpli?d schematic of the reference circuit is shown in fig- ure 14. a single external resistor connected between the ref pin and v ee determines the output current for all output stages. this feature allows a choice of pull-up networks and transmission line characteristic impedances while still achieving a nominal output swing of 800 mv. at low data ra tes, substantial power savings can be achieved by using lower output swings and higher load resistances. AD8151 v ee r set ref v cc i out /20 1.2v figure 14. simpli?d reference circuit the nominal output current is given by the following expression: i v r out set = ? ? ? ? ? ? 20 12 . the minimum set resistor is r set,min = 960 ? resulting in i out,max = 25 ma. the maximum set resistor is r set,max = 4.8 k ? resulting in i out,min = 5 ma. nominal 800 mv differen- tial output swing can be ac hieved in a 50 ? load using r set = 1.5 k ? (i out = 16 ma), or in a doubly-terminated 75 ? load using r set = 1.13 k ? (i out = 21.3 ma). to minimize stray capacitance and avoid the pickup of unwanted signals, the external set resistor should be located close to the ref pin. bypassing the set resistor is not recommended.
AD8151 ?9 rev. 0 power supplies there are several options for the power supply voltages for the AD8151, as there are two separate sections of the chip that require power supplies. these are the control logic and the high-speed data paths. depending on the system architecture, the voltage levels of these supplies can vary. logic supplies the control (programming) logic is cmos and is designed to interface with any of the various standard single-ended logic families (cmos or ttl). its supply voltage pins are v dd (pin 170, logic positive) and v ss (pin 152, logic ground). in all cases the logic ground should be connected to the system digital ground. v dd should be supplied at between 3.3 v to 5 v to match the supply voltage of the logic family that is used to drive the logic inputs. v dd should be bypassed to ground with a 0.1 f ceramic capacitor. the absolute maximum voltage from v dd to v ss is 5.5 v. data path supplies the data path supplies have more options for their voltage lev- els. the choices here will affect several other areas, like power dissipation, bypassing, and common mode levels of the inputs and outputs. the more positive voltage supply for the data paths is v cc (pins 41, 98, 149 and 171). the more negative supply is v ee , which appears on many pins that will not be listed here. the maximum allowable voltage across these supplies is 5.5 v. the rst choice in the data path power supplies is to decide whether to run the device as ecl (emitter-coupled logic) or pecl (positive ecl). for ecl operation, v cc will be at ground potential, while v ee will be at a negative supply between 3.3 v to 5 v. this will make the common-mode voltage of the inputs and outputs at a negative voltage, see figure 15. data paths control logic +3.3v to +5v C 3.3v to C 5v v ss v ee gnd gnd 0.1 f (one for every two v ee pins) 0.1 f AD8151 v dd v cc figure 15. power supplies and bypassing for ecl operation if the data paths are to be dc-coupled to other ecl logic devices that run with ground as the most positive supply and a negative voltage for v ee , then this is the proper way to run. however, if the part is to be ac-coupled, it is not necessary to have the input/ output common mode at the same level as the other system circuits, but it will probably be more convenient to use the same supply rails for all devices. for pecl operation, v ee will be at ground potential and v cc will be a positive voltage from 3.3 v to 5 v. thus, the common mode of the inputs and outputs will be at a positive voltage. these can then be dc-coupled to other pecl operated devices. if the data paths are ac-coupled, then the common-mode levels do not matter, see figure 16. data paths control logic +3.3v to +5v +3.3v to +5v v ss v ee gnd gnd 0.1 f (one for each v cc pin, 4 required) 0.1 f AD8151 v dd v cc figure 16. power supplies and bypassing for pecl operation power dissipation for analysis, the power dissip ation of the AD8151 can be divided into three separate parts. these are the control logic, the data path circuits and the (ecl or pecl) outputs, which are part of the data path circuits, but can be dealt with separately. the rst of these, the control logic, is cmos technology and does not dissipate a signi cant amount of power. this power will, of course, be greater when the logic supply is 5 v rather than 3 v, but overall it is not a signi cant amount of power and can be ignored for thermal analysis. data paths control logic v ss v ee gnd gnd AD8151 v dd v cc i, data path logic v out low C v ee r out i out figure 17. major power consumption paths the data path circuits operate between the supplies v cc and v ee . as described in the power supply section, this voltage can range from 3.3 v to 5 v. the current consumed by this section will be constant, so operating at a lower voltage can save about 35 percent in power dissipation.
AD8151 ?0 rev. 0 the power dissipated in the data path outputs is affected by several factors. the rst is whether the outputs are enabled or disabled. the worst case occurs when all of the outputs are enabled. the current consumed by the data path logic can be approxi- mated by: i cc = 35 ma + [4.5 ma + ( i out /20 ma 3 ma )] (# of outputs enabled ) this says that there will always be a minimum of 35 ma flow- ing. i cc will increase by a factor that is proportional to both the number of enabled outputs and the programmed output current. the power dissipated in this circuit section will simply be the voltage of this section (v cc v ee ) times the current. for a worst case, assume that v cc v ee is 5.0 v, all outputs are enabled and the programmed output current is 25 ma. the power dissi- pated by the data path logic will be: p = 5.0 v {35 ma + [4.5 ma + (25 ma /20 ma 3 ma )] 17} = 876 mw the power dissipated by the output current depends on several factors. these are the programmed output current, the voltage drop from a logic low output to v ee and the number of enabled outputs. a simplifying assumption is that one of each (enabled) differential output pair will be low and draw the full output current (and dissipate most of the power for that output), while the complementary output of the pair will be high and draw insigni cant current. thus, its power dissipation of the high output can be ignored and the output power dissipation for each output can be assumed to occur in a single static low output that sinks the full output-programmed current. the voltage across which this current flows can also vary, depend- ing on the output circuit design and the supplies that are used for the data path circuitry. in general, however, there will be a voltage difference between a logic low signal and v ee . this is the drop across which the output current flows. for a worst case, this voltage can be as high as 3.5 v. thus, for all outputs enabled and the programmed output current set to 25 ma, the power dissipated by the outputs: p = 3.5 v (25 ma ) 17 = 1.49 w heat sinking depending on several factors in its operation, the AD8151 can dissipate upwards of 2 w or more. the part is designed to oper- ate without the need for an explicit external heatsink. however, the package design offers enhanced heat removal via some of the package pins to the pc board traces. the v ee pins on the input sides of the package (pins 1 to 46 and pins 93 to 138) have nger extensions inside the package that connect to the paddle upon which the ic chip is m ounted. these pins provide a lower thermal resistance from the ic to the v ee pins than other pins that just have a bond wire. as a result these pins can be used to enhance the heat removal pro- cess from the ic to the circuit board and ultimately to the ambient. the v ee pins described above should be connected to a large area of circuit board trace material in order to take most advantage their lower thermal resistance. if there is a large area available on an inner layer that is at v ee potential, then vias can be pro- vided from the package pin traces to this layer. there should be no thermal-relief pattern when connecting the vias to the inner layers for these v ee pins. additional vias in parallel and close to the pin leads can provide an even lower thermal resistive path. if possible to use, 2 oz. copper foil will provide better heat removal than 1 oz. the AD8151 package has a speci ed thermal impedance ja of 30 c/w. this is the worst case, still-air value that can be expected when the circuit board does not signi cantly enhance the heat removal from the package. by using the concept described above or by using forced-air circulation, the thermal impedance can be lowered. for an extreme worst case analysis, the junction rise above the ambient can be calculated assuming 2 w of power dissipation and ja of 30 c/w to yield a 60 c rise above the ambient. there are many techniques described above that can mitigate this situa- tion. most actual circuits will not result in this high a rise of the junction temperature above the ambient. applications AD8151 input and output busing although the AD8151 is a digital part, in any application that runs at high speed, analog design details will have to be given very careful consideration. at high data rates, the design of the signal channels will have a strong influence on the data integrity and its associated jitter and ultimately bit error rate (ber). while it might be considered very helpful to have a suggested circuit board layout for any particular system con guration, this is not something that can be practically realized. systems come in all shapes, sizes, speeds, performance criteria and cost constra ints. therefore, some general design guidelines will be presented t hat can be used for all systems and judiciously modi- ed where appropriate. high-speed signals travel best, i.e. maintain their integrity, when they are carried by a uniform transmission line that is properly terminated at either end. any abrupt mismatches in impedance or improper termination will create reflections that will add to or subtract from parts of the desired signal. small amounts of this effect are unavoidable, but too much will distort the signal to the point that the channel ber will increase. it is dif cult to fully quantify these effects, because they are influenced by many factors in the overall system design. a constant-impedance transmission line is characterized by having a uniform cross-section pro le over its entire length. in particular, there should be no stubs, which are branches that intersect the main run of the transmission line. these can have an electrical appearance that is approximated by a lumped element, such as a capacitor, or if long enough, as another trans- mission line. to the extent that stubs are unavoidable in a design, their effect can be minimized by making them as short as pos- sible and as high an impedance as possible. figure 13 shows a differential transmission line that connects two differential outputs from AD8151s to a generic receiver. a more generalized system can have more outputs bused, and more receivers on the same bus, but all the same concepts apply. the inputs of the AD8151 can also be considered as a receiver. the transmission lines that bus all of the devices together are shown with terminations at each end. the individual outputs of the AD8151 are stubs that intersect the main transmission line. ideally, their current-source outputs would be in nite impedance, and they would have no effect on signals that propagate along the transmission line. in reality, each
AD8151 ?1 rev. 0 external pin of the AD8151 projects into the package, and has a bond wire connected to the chip inside. on-chip wiring then connects to the collectors of the output transistors and to esd protection diodes. unlike some other high-speed digital components, the AD8151 does not have on-chip terminations. while this location would be closer to the actual end of the transmission line for some architectures, this concept can limit system design options. in particular, it is not possible to bus more than two inputs or outputs on the same transmission line and it is also not possible to change the value of these terminations to use for different impedance transmission lines. the AD8151, with the added ability to disable its outputs, is much more versatile in these types of architectures. if the external traces are kept to a bare minimum, then the output will present a mostly lumped capacitive load of about 2 pf. a single stub of 2 pf will not seriously adversely affect signal integrity for most transmission lines, but the more of these stubs, the more adverse their influence will be. one way to mitigate this effect is to locally reduce the capacitance of the main transmission line near the point of stub intersection. some practical means for doing this are to narrow the pc board traces in the region of the stub and/or to remove some of the ground plane(s) near this intersection. the effect of these tech- niques will locally lower the capacitance of the main transmission line at these points, while the added capacitance of the AD8151 outputs will compensate for this reduction in capacitance. the overall intent is to create as uniform a transmission line as possible. in selecting the location of the termination resistors it is impor- tant to keep in mind that, as their name implies, they should be placed at either end of the line. there should be no or minimal projection of the transmission line beyond the point where the termination resistors connect to it. evaluation board an evaluation board has been designed and is available to rapidly test the main features of the AD8151. this board lets the user analyze the analog performance of the AD8151 channels and easily control the configuration of the board by a standard pc. the board has limited numbers of differential input/output pairs. each differential pair of microstrip is connected to either top-mount or side-launch sma connectors. the top-mount sma connectors are drilled and stubbed for superior perfor- mance. the fr4 type board contains a total of nine outputs (all even numbered outputs) and 20 inputs (numbers 0, 2, 4, 6, 8, 10, 12, 13, 14, 15, 16, 17, 18, 20, 22, 24, 26, 28, 30, 32). it is important to note that the shells of the sma connectors are attached to vcc. this makes only ecl or negative level swings possible during testing. power supplies the AD8151 is des igned to work with standard ecl logic levels. this means that v cc is at ground and v ee is at a negative supply. the shells of the i/o sma connectors are at v cc potential. thus, when operating in the standard ecl configuration, test equipment can be directly connected to the board, as the test equipment will have its connector shells at ground potential also. operating in pecl mode requires v cc to be at a positive volt- age, while v ee is at ground. since this would make the shells of the i/o connectors at a positive voltage, it can cause problems when directly connecting to test equipment. some equipment, such as battery-operated oscilloscopes, can be floated from ground, but care should be taken with line-powered equipment to avoid creating a dangerous situation. refer to the manual of the test equipment that is being used. the voltage difference from v cc to v ee can range from 3 v to 5 v. power savings can be realized by operating at a lower volt- age without any compromise in performance. a separate connection is provided for v tt , the termination potential of the outputs. this can be at a voltage as high as v cc , but power savings can be realized if v tt is at a voltage that is somewhat lower. please consult elsewhere in the data sheet for the specification for the limits of the v tt supply. as a practical matter, current on the evaluation board will flow from the v tt supply, through the termination resistors, into the multiple outputs of the AD8151, and on to the v ee supply. when running in ecl mode, v tt will want to be at a negative supply. most power supplies will not allow their ground connection to v cc and then the negative supply to v tt . this will require them to source current from their negative supply, which wants to flow to the more-negative v ee . this current will not then return to the ground terminal of the v tt supply. thus, v tt should be referenced to v ee when running in ecl mode or a true bipolar supply should be used. the digital supply is provided to the AD8151 by the v dd and v ss pins. v ss should always be at ground potential to make it compatible with standard cmos or ttl logic. v dd can range from 3 v to 5 v, and should be matched to the supply voltage of the logic used to control the AD8151. however, s ince pcs use 5 v logic on their parallel port, v dd should be at 5 v when using a pc to program the AD8151. bypassing most of the board s bypass capacitors are opposite the dut on the solder side, connected between v cc and v ee . this is where they will be most effective. these capacitors are 0.01 f ceramic chip capacitors for low inductance. there are additional higher value capacitors elsewhere on the board for bypassing at lower frequencies. the location of these is not as critical. input and output considerations each input contains a 100 ? differential termination. although the differential termination eases board layout due to its c ompact nature, it can cause problems with the driving generator. a typical pulse or pattern generator wants to see 50 ? to ground (or to 2 v in some cases). high speed probing of the input showed if this type of termination is not present then input amplitudes could be slightly off. even more affected can be the dc input levels. depending on the generator used, these levels can be off as much as 800 mv in either direction. a correction for this problem is to attach a 6 db attenuator to each p and n input. because the AD8151 has a large common-mode voltage range on its input stage, it will not be significantly affected by dc level errors.
AD8151 ?2 rev. 0 on this evaluation board all unused inputs are tied to v cc (gnd). all outputs, whether brought out to connectors or not, are tied to v tt through a 49.9 ? resistor. the AD8151 device is on the component side of the board, while input terminations and output back terminations are on the circuit side. the input signals from the circuit side transit through via holes to the dut s pads. the component-side output signals connect to via holes and to circuit-side 49.9 ? termination resistors. board construction for this board fr4 material was chosen over more exotic board materials. tests showed exotic materials to be unnecessary. this is a 4-layer board. power is bused on both external and internal layers. test structures showed microstrip performance to be unaffected by the dc bias levels on the plane beneath it. the manufacturing process should produce a controlled- impedance board. the board stack consists of a 5-mil-thick layer between external and internal layers. this allows the use of an 8-mil-wide microstrip trace running from sma connector to the dut s pads. the narrow trace avoids the need to neck down the trace width as dut s pads are approached and it helps to control the microstrip trace impedance. the thin 5-mil dielec tric also helps to control crosstalk by way of confining the electro- magnetic fields more between the trace and the plane below. configuration programming the board is configurable by one of two methods. for ease of use, custom software is provided that controls the AD8151 programming via the parallel port of a pc. this requires a user- supplied standard printer cable that has a db-25 connector at one end (parallel- or printer-port interface) and a centronix- type connector at the other that connects to p2 of the AD8151 evaluation board. the programming with this scheme is done in a serial fashion, so it is not the fastest way to configure the AD8151 matrix. however, the user interface makes it very convenient to use this programming method. if a high-speed programming interface is desired, the AD8151 address and data buses are directly available on p3. the source of the program signals can be a piece of test equipment, like the tektronix hfs-9000 digital test generator, or some other user- supplied hardware that generates programming signals. when using the pc interface, the jumper at w1 should be installed and no connections should be made to p3. when using the p3 interface, no jumper is installed at w1. there are loca- tions for termination resistors for the address and data signals if these are necessary. software installation the software to operate the AD8151 is provided on two 3.5" floppy disks. the software is installed by inserting disk 1 into the floppy drive of a pc and running the setup.exe program. this will routinely install the software and prompt the user when to change to disk 2. the setup program will also prompt the user to select the directory for the program. after running the software, the user will be prompted to identify which (of three) software driver is used with the pc s parallel port. the default is lpt1, which is most commonly used. how- ever, some laptops commonly use the prn driver. it is also possible that some systems are configured with the lpt2 driver. if it is not known which driver is used, it is best to select lpt1 and proceed to the next screen. this will show a full array of buttons that allows the connection of any input to output of the AD8151. all of the outputs should be in the output off state right after the program starts running. any of the active buttons can be selected with a mouse click, which will send out one burst of programming data. after this, the pc keyboard s left or right arrow keyboard key can be held down to generate a steady stream of programming signals out of the parallel port. the clock test point on the AD8151 evaluation board can be monitored with an oscillo- scope for any activity (user-supplied printer cable must be connected). if there is a square-wave present, the proper soft- ware driver is selected for the pc s parallel port. if there is no signal present, another driver should be tried by selecting the parallel port menu item under the file pull- down menu selection just under the title bar. select a different software driver and carry out the above test until signal activity is present at the clock test point. software operation any button can be clicked in the matrix to program the input to output connec tion. this will send the proper programming sequence out the pc parallel port. since only one input can be programmed to a given output at one time, clicking a button in a horizontal row will cancel the other selection that is already selected in that row. however, any number of outputs can share the same input. a shortcut for programming all outputs to the same input is to use the broadcast feature. after clicking on the broadcast con- nection button, a screen will appear that will prompt for the user to select which input should be connected to all outputs. the user should type in an integer from 0 to 32 and then click on ok. this will send out the proper program data and return to the main screen with a full column of buttons selected under the chosen input. the off column can be used to disable to whichever output one chooses. to disable all outputs, the global reset button can be clicked. this will select the full column of off buttons. two scratch-pad memories (memory 1 and memory 2) are provided to conveniently save a particular configuration. how- ever, these registers are erased when the program is terminated. for long-term storage of configurations, the disk-storage memory should be used. the save and load selections can be accessed from the file pull-down menu under the title bar.
AD8151 ?3 rev. 0 AD8151 figure 18. evaluation board controller
AD8151 ?4 rev. 0 figure 19. component side
AD8151 ?5 rev. 0 figure 20. circuit side
AD8151 ?6 rev. 0 figure 21. silkscreen top
AD8151 ?7 rev. 0 figure 22. soldermask top
AD8151 ?8 rev. 0 figure 23. silkscreen bottom
AD8151 ?9 rev. 0 figure 24. soldermask bottom
AD8151 ?0 rev. 0 figure 25. int1 (v ee )
AD8151 ?1 rev. 0 figure 26. int2 (v cc )
AD8151 ?2 rev. 0 122 130 129 127 128 123 124 125 126 121 137 138 132 133 134 135 131 136 120 118 119 116 117 113 114 115 111 112 109 110 108 105 106 107 104 102 103 100 101 95 96 97 98 99 93 94 59 47 48 49 50 51 52 53 54 55 56 57 58 60 61 62 63 64 65 66 67 68 69 70 71 72 74 75 76 77 78 73 79 80 81 82 84 85 86 87 83 88 89 90 91 92 14 13 12 11 16 15 17 10 19 18 23 22 21 20 25 24 27 26 29 28 32 31 30 34 33 36 35 39 38 37 40 41 43 42 45 44 46 5 4 3 2 7 6 9 8 1 top view (not to scale) pin 1 identifier 184 183 182 181 180 179 178 177 176 175 174 173 171 170 169 168 167 166 165 164 163 162 172 161 160 159 157 156 155 154 153 152 158 151 150 149 147 146 145 144 143 142 141 140 139 148 in19n in19p in18n in18p in17n in17p in16n in16p v dd reset cs re we update a0 a1 a2 a3 a4 d0 d1 d2 d3 d4 d5 d6 in15n in15p in14n in14p in13n in13p r203 1.5k c13 0.01 f v cc c29 0.01 f v ee out15n out15p out14n out14p out13n out13p out12n out12p out11n out11p out10n out10p out09n out09p out08n out08p out07n out07p out06n out06p out05n out05p out04n out04p out03n out03p out02n out02p out01n out01p v ee in20p in20n in21p in21n in22p in22n in23p in23n in24p in24n in25p in25n in26p in26n in27p in27n in28p in28n in29p in29n in30p in30n in31p in31n in32p in32n out16n out16p c11 0.01 f v ee v cc c15 0.01 f v ee in12n in12p v ee in11n in11p in10n in10p in09n in09p in08n in08p in07n in07p in06n in06p in05n in05p in04n in04p in03n in03p in02n in02p in01n in01p in00n in00p out00p out00n c60 0.01 f v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v cc AD8151 184l lqfp v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v cc v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee v ee c31 0.01 f v ee v cc c32 0.01 f v cc v ee v ee v ee v ee v cc v cc c4 0.01 f v ee v cc c5 0.01 f v ee c7 0.01 f v ee v cc c6 0.01 f v ee v cc v dd c14 0.01 f v ss c30 0.01 f v ee v cc c10 0.01 f v ee v cc c9 0.01 f v ee v cc c8 0.01 f v ee v cc v cc c12 0.01 f v ee figure 27. bypassing schematic
AD8151 ?3 rev. 0 p52 p53 r93 105 in24p in24n r94 1.65k r92 1.65k v cc v ee p16 p17 r39 105 in06p in06n r40 1.65k r38 1.65k v cc v ee v cc p4 p5 v ee r20 105 in00p in00n r19 1.65k r21 1.65k p28 p29 r57 105 in12p in12n r58 1.65k r56 1.65k v cc v ee p40 p41 r90 105 in18p in18n r89 1.65k r91 1.65k v cc v ee p64 p65 r117 105 in30p in30n r116 1.65k r118 1.65k v cc v ee p56 p57 r99 105 in26p in26n r98 1.65k r100 1.65k v cc v ee p20 p21 r45 105 in08p in08n r44 1.65k r46 1.65k v cc v ee p8 p9 r27 105 in02p in02n r28 1.65k r26 1.65k v cc v ee p32 p33 r63 105 in14p in14n r62 1.65k r64 1.65k v cc v ee p44 p45 r84 105 in20p in20n r85 1.65k r83 1.65k v cc v ee p68 p69 r111 105 in32p in32n r112 1.65k r110 1.65k v cc v ee p60 p61 r105 105 in28p in28n r104 1.65k r106 1.65k v cc v ee p24 p25 r51 105 in10p in10n r50 1.65k r52 1.65k v cc v ee p12 p13 r33 105 in04p in04n r34 1.65k r32 1.65k v cc v ee p36 p37 r69 105 in16p in16n r68 1.65k r70 1.65k v cc v ee p48 p49 r78 105 in22p in22n r79 1.65k r77 1.65k v cc v ee p30 p31 r60 105 in13p in13n r59 1.65k r61 1.65k v cc v ee p34 p35 r66 105 in15p in15n r65 1.65k r67 1.65k v cc v ee p38 p39 r72 105 in17p in17n r71 1.65k r73 1.65k v cc v ee v cc p n in01, in03, in05, in07, in09, in11, in19, in21, in23, in25, in27, in29, in31 p103 p102 r121 49.9 out00n r122 49.9 out00p v tt p87 v tt r160 49.9 out08n r162 49.9 p86 out08p v cc v tt c16 0.01 f v cc v tt c82 0.01 f v cc v tt c83 0.01 f p71 r200 49.9 out16n r198 49.9 p70 out16p v tt out15n out15p v tt r190 49.9 r192 49.9 out07n out07p r155 49.9 r153 49.9 v tt p91 r150 49.9 out06n r152 49.9 p90 out06p v tt p75 r195 49.9 out14n r193 49.9 p74 out14p v tt r180 49.9 out13n r182 49.9 out13p v tt r145 49.9 out05n r143 49.9 out05p v tt p95 r140 49.9 out04n r142 49.9 p94 out04p v tt p79 r185 49.9 out12n r183 49.9 p78 out12p v tt r170 49.9 out11 n r172 49.9 out11p v tt r135 49.9 out03n r133 49.9 out03p v tt p99 r130 49.9 out02n r132 49.9 p98 out02p v tt p83 r175 49.9 out10n r173 49.9 p82 out10p v tt v tt r165 49.9 out09n r163 49.9 out09p r125 49.9 out01n r127 49.9 out01p v tt figure 28. evaluation board input/output schematic
AD8151 ?4 rev. 0 + v tt p1 6 v cc p1 1 p1 2 v ee p1 3 v dd p1 4 p1 7 v ss p1 5 c3 10 f c1 10 f v tt v tt v cc v cc v ee v ee + v dd + c2 10 f v ss p104 p105 out_en d0 d1 d2 d3 d4 d5 d6 d7 1 2 3 4 5 6 7 8 9 gnd 10 v cc q0 q1 q2 q3 q4 q5 q6 q7 20 19 18 17 16 15 14 13 12 clk 11 r12 49.0 v ss v ss r13 49.0 r14 49.0 v ss v ss r15 49.0 r16 49.0 v ss read p2 7 reset p2 3 write p2 8 update p2 4 chip_select p2 2 write p3 13 reset p3 7 read p3 11 d0 p3 27 a4 p3 25 a3 p3 23 a2 p3 21 a1 p3 19 a0 p3 17 d6 p3 39 d5 p3 37 d4 p3 35 d3 p3 33 d2 d1 p3 29 update p3 15 chip_select p3 9 v dd p3 5 v ss p3 14 p3 8 p3 12 p3 28 p3 26 p3 24 p3 22 p3 20 p3 18 p3 40 p3 38 p3 36 a2 data p2 5 clk p2 6 clk data v ss p2 25 v dd v ss v dd c86 0.1 f v ss v dd c87 0.1 f v ss v dd c88 0.1 f v ss v dd c89 0.1 f v ss a1, 4 pin 14 is tied to v dd . a1, 4 pin 7 is tied to v ss . r7 49.0 v ss v ss v ss v ss v ss out_en d0 d1 d2 d3 d4 d5 d6 d7 1 2 3 4 5 6 7 8 9 gnd 10 v cc q0 q1 q2 q3 q4 q5 q6 q7 20 19 18 17 16 15 14 13 12 clk 11 p3 31 a4 p3 34 p3 32 p3 30 p3 16 p3 10 p3 6 v dd v ss a3 v dd tp5 tp4 tp6 tp7 tp8 chip_select 168 update 165 write 166 reset 169 read 167 a4 74hc132 74hc132 r1 20k 1 2 4 5 w1 v ss 74hc14 a1 74hc14 a1 74hc14 a1 1 2 3 4 5 6 74hc74 74hc74 160a4 161a3 162a2 163a1 164a0 tp9 tp10 tp11 tp12 tp13 tp20 tp14 tp15 tp16 tp17 tp18 tp19 153d6 154d5 155d4 156d3 157d2 158d1 159d0 v dd v ss v ss v dd v dd 9 10 8 a4 a1 11 10 a1 13 12 12 13 11 a4 v dd 74hc14 a1 9 8 74hc14 74hc14 74hc132 74hc132 r8 49.0 r9 49.0 r11 49.0 r10 49.0 v ss r17 49.0 r18 49.0 v ss r2 49.0 v ss v ss r3 49.0 r4 49.0 v ss v ss r5 49.0 r6 49.0 v ss 3 6 figure 29. evaluation board logic controls
AD8151 ?5 rev. 0 outline dimensions dimensions shown in mm and (inches). 184-lead plastic lqfp (st-184) 139 138 47 46 92 93 186 pin 1 top view (pins down) 1 0.40 (0.016) bsc 0.23 (0.009) 0.18 (0.007) 0.13 (0.005) 20.00 (0.787) bsc sq 22.00 (0.866) bsc sq seating plane 0.08 (0.003) 0.15 (0.006) 0.05 (0.002) 1.60 (0.063) max 0.75 (0.030) 0.60 (0.024) 0.45 (0.018) 1.45 (0.057) 1.40 (0.053) 1.35 (0.048) controlling dimensions are in millimeters
?6 c02169?.5?/01(0) printed in u.s.a.

▲Up To Search▲

Price & Availability of AD8151

	To Download AD8151 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .